Advanced complex semiconductor device design and manufacturing has matured to a high level of quality mandated by the complexity of process steps, device circuit density, and the device minimum feature size. Consequently, many design considerations must be considered in the design of advanced complex semiconductor devices, including power dissipation, timing performance, and leakage power, among others. In response, layout, electrical simulation, and many other related activities have been integrated into full-fledged electronic device design systems. Such electronic design systems enable integrated circuit (IC) designers to fabricate complex structures within a computerized virtual environment, wherein complex three dimensional cells may be constructed, electrically simulated, and matched against manufacturing process capabilities.
However, challenges still exist in designing and maintaining performance of devices, particularly as device dimensions continue to decrease. For example, electrical performance degradation can occur due to the increased density of interconnects and logical devices. To assist in the development of such devices, the layout of developing designs can comprise myriad basic or standard cell-structures that the IC designer can utilize in an electronic design layout system. The myriad standard device cells can include generally employed or frequently used cells comprised of different configurations of field effect transistors (FETS), conductive interconnect configurations, and a plurality of other structures well known by one skilled in the art.
One of the major challenges faced during the development of new designs is the reduction of standby leakage power. Standby leakage power can be associated with any electrical leakage that may occur while an FET or other cell component is not electrically activated. The standby electrical leakage can contribute to degradation in device performance.